1. Field of the Invention
The present invention relates to a semiconductor device having a redistribution layer.
2. Description of Related Art
System-in-package (SiP) technology for configuring a system of plural semiconductor chips (hereinafter referred to as “chips”) sealed in a package has been known. A SiP includes plural ready-made chips stacked or horizontally arranged and sealed in a package. Depending on the arrangement of pads formed on each chip, therefore, routing of wires to be bonded becomes complicated to possibly cause bonded wires to come into mutual contact. To avoid this problem, it sometimes becomes necessary to change pad locations on individual chips before mounting chips for sealing as a SiP.
Redistribution layer (hereinafter referred to as “RDL”) technology is among the means of changing pad locations. In RDL technology, a redistribution layer is formed over an existing chip. A redistribution layer includes appropriately located new pads and redistribution lines for coupling pads formed over an existing chip and the new pads. The pads formed over a chip can be appropriately relocated making use of a redistribution layer formed over the chip. There is, however, a problem with this technology. That is, circuits and signal lines formed over the existing chip are adversely affected by electric field noise generated by electric current flowing through the pads and redistribution lines formed over the redistribution layer. Technology for solving the above problem is disclosed in Japanese Unexamined Patent Publication No. 2005-005741.
FIG. 1 is a sectional view of the semiconductor device disclosed in Japanese Unexamined Patent Publication No. 2005-005741. The semiconductor device includes metallic parts 150 formed over the uppermost layer of a multilayer wiring layer 120 formed over a substrate 110 over which capacitors 101 are formed. The multilayer wiring layer 120 includes plural stacked layers each insulated with an interlayer insulation film 130 and a wiring 140 formed over each of the stacked layers. External terminals 400 and redistribution lines 500 are formed over an insulation film 300 which is formed over the multilayer wiring layer 120. Each external terminal 400 is coupled to an electrode 200 of a semiconductor chip 100 by a redistribution line 500.
FIG. 2 is a plan view of the semiconductor device disclosed in Japanese Unexamined Patent Publication No. 2005-005741. Each metallic part 150 is formed in a region not included in any region where a wiring 140 is formed and is positioned upward of a capacitor 101 (or an analog circuit). Each metallic part 150 is electrically coupled to a node 200 kept at a predetermined potential.
In the semiconductor device disclosed in Japanese Unexamined Patent Publication No. 2005-005741, the electric field noise generated by the external terminals 400 and redistribution lines 500 formed over the redistribution layer is shielded by the metallic parts 150. Therefore, the possibility of the capacitors 101 being affected by the electric field noise can be reduced. Also, since the metallic parts 150 can be formed in an existing process of forming the multilayer wiring layer 120, they can be formed without largely increasing the total production processes.